1. Field of the Invention
The present invention relates to a method of operating a dynamic random access memory (DRAM), and more particularly to a method of operating a DRAM without using a charge pump.
2. Description of Related Art
Dynamic random access memory (DRAM) has been widely used in a variety of electronic products, such as computers, memory cards or related products. FIG. 1 is a schematic drawing showing a prior art memory cell array of DRAM. In the prior art design, a memory cell comprises a switch device 100 and a charge storage device 110. The charge storage device 110 is coupled to the bit line BL or the bit line bar BLB via the switch device 100. The switch device 100 is either a P-type or an N-type metal oxide semiconductor (MOS) device and can be controlled via the voltage of the word lines WL0–WL3.
In the conventional operating method of DRAM, the voltage at the point (called memory point thereafter) 120 represents the data stored in the memory cell where the charge storage device 110 is coupled to the switch device 100 at the memory point 120. Generally, when the data is logic 0, the voltage of the memory point 120 is pulled down to zero voltage. When the data is logic 1, the voltage of the memory point 120 is pulled up to the power voltage VDD. During the reading operation, the bit line BL and the bit line bar BLB are charged to the same voltage, e.g. one half of the power voltage VDD. In order to turn on the switch device 100, the word line WL0 is charged to the voltage VPP, which is about VDD+VTN+0.3V, wherein VTN represents the threshold voltage of the switch device 100. After the switch device 100 is turned on, the voltage of the bit line BL is changed because voltage is being shared with the charge storage device 110 hence the sensor of DRAM senses the voltages of the bit line BL and the bit line bar BLB. The data stored in the memory cell can then be identified by the voltage differences.
FIG. 2 is a circuit block diagram showing a prior art driving circuit of DRAM. The operation of the DRAM 20 is similar to that described above. However, there is a disadvantage in the prior art DRAM. In order to provide the voltage VPP, which is higher than the normal power voltage, a charge pump 200 is applied in the driving circuit of the DRAM shown in FIG. 2. Since the bit line BL and the bit line bar BLB have to be charged to one half of the power voltage VDD, DRAM 20 has to supply direct voltage of VDD/2. Because of the charge pump 200 and the additional direct voltage, the DRAM 20 consumes powers even when it is in stand-by mode. The power consumption shortens the service life of cells of portable devices.